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rev. 0.3 4/10 copyright ? 2010 by silicon laboratories si823x this information applies to a product under development. its characteristics and specifications are subject to change without n otice. si823x 0.5 and 4.0 a mp iso drivers (2.5 and 5 k v rms ) features applications description the si823x isolated driver family combines two independent, isolated drivers into a single package. th e SI8230/1/3/4 are high-side/low-side drivers, and the si8232/5/6 are dual drivers. versions with peak output currents of 0.5 a (SI8230/1/2) and 4. 0 a (si8233/4/5/6) are available. all drivers operate with a maximum supply voltage of 24 v. the si823x drivers utilize silicon l abs' proprietary silicon isolation technology, which provides up to 5 kv rms withstand voltage per ul1577, and fast 60 ns propagation times. driver outputs can be grounded to the same or separate grounds or connected to a positive or negative voltage. the ttl level compatible inputs with >400 mv hysteresis are available in individual control input (SI8230/ 2/3/5/6) or pwm input (si8231/4) configurations. high integration, low propagation delay, small installed size, flexibility, and cost-effectivene ss make the si823x family ideal for a wide range of isolated mosfet/igbt gate drive applications. safety approval ? two completely isolated drivers in one package ?? up to 5 kv rms input-to-output isolation ?? up to 1500 v dc peak driver-to- driver differential voltage ? hs/ls and dual driver versions ? up to 8 mhz switching frequency ? 0.5 a peak output (SI8230/1/2) ? 4.0 a peak output (si8233/4/5/6) ? 60 ns maximum propagation delay ? independent hs and ls inputs or pwm input versions ? transient immunity >30 kv/s ? overlap protection and programmable dead time ? operating temperature range ?40 to +125 c ? ul/vde/csa approval ? rohs-compliant ? power delivery systems ? motor control systems ? isolated dc-dc power supplies ? lighting control systems ? plasma displays ? solar and industrial inverters ? ul 1577 recognized ?? up to 5000 vrms for 1 minute ? csa component notice 5a approval ?? iec 60950, 61010, 60601 (reinforced insulation) ? vde certification conformity ?? iec 60747-5-2 (vde 0884 part 2) ?? en 60950 (reinforced insulation) (pending) patents pending pin assignments via vib vddi gndi disable dt nc vddi vdda voa gnda nc nc vddb vob gndb SI8230 si8233 soic-16 (wide) via vib vddi gndi disable dt nc vddi vdda voa gnda nc nc vddb vob gndb SI8230 si8233 soic-16 (narrow) lga-14 (5 x 5 mm) gndi via vib vddi disable dt vddi vdda voa gnda nc vddb vob gndb SI8230 si8233 1 2 3 4 5 6 7 8 9 12 11 10 13 14 15 16 1 2 3 4 5 6 7 8 9 12 11 10 13 14 15 16 1 2 3 4 5 6 7 14 13 12 11 10 7 8 free datasheet http:///
si823x 2 rev. 0.3 block diagrams gndi vib vddi via vdda voa gnda vob vddb gndb disable dt uvlo isolation isolation gndi vddi pwm vdda voa gnda vob vddb gndb disable dt uvlo isolation isolation gndi vddi via vdda voa gnda vob vddb gndb disable uvlo isolation isolation vib overlap protection, programmable dead time, control gating programmable dead time, control gating control gating SI8230/3 si8231/4 si8232/5/6 free datasheet http:///
si823x rev. 0.3 3 t able of c ontents section page 1. top-level block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 2.1. test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 2.2. theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3. typical operating characteristics (0.5 amp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4. typical operating characteristics (4.0 amp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5. application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 5.1. products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.2. device behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 5.3. power supply connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.4. power dissipation considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 5.5. layout considerat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.6. device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.7. programmable dead time and overlap protection . . . . . . . . . . . . . . . . . . . . . . . . . 26 6. rf radiated emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8 6.1. rf, magnetic, and comm on mode transient immunity . . . . . . . . . . . . . . . . . . . . . . 28 7. applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.1. high-side / low-side dr iver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.2. dual driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 7.3. dual driver with thermally enhanced package (si8236) . . . . . . . . . . . . . . . . . . . . .30 8. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10. package outline: 16-pi n wide body soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 11. land pattern: wide-body soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 12. package outline: narrow body soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 13. land pattern: narrow body soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 14. package outline: 14 ld lga (5 x 5 mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 15. land pattern: 14 ld lga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 16. package outline: 14 ld lga with thermal pad (5 x 5 mm) . . . . . . . . . . . . . . . . . . . . .48 17. land pattern: 14 ld lga with thermal pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 free datasheet http:///
si823x 4 rev. 0.3 1. top-level block diagrams figure 1. SI8230/3 two-input high-side / low-side isolated drivers figure 2. si8231/4 single-input high-side / low-side isolated drivers SI8230/3 uvlo uvlo gndi vib vddi via vdda voa gnda vob vddi vddi isolation vddi vddb gndb disable isolation uvlo dt control & overlap protection dt si8231/4 uvlo uvlo gndi vddi pwm vdda voa gnda vob vddi vddi isolation vddi vddb gndb disable isolation uvlo dt control & overlap protection dt lpwm lpwm free datasheet http:///
si823x rev. 0.3 5 figure 3. si8232/5/6 dual isolated drivers si8232/5/6 uvlo vdda voa gnda vob vddi isolation vddi vddb gndb uvlo via isolation uvlo gndi vib vddi vddi disable free datasheet http:///
si823x 6 rev. 0.3 2. electrical specifications table 1. electrical characteristics 1 4.5 v < vddi < 5.5 v, vdda = vddb = 12 v or 15 v. ta = ?40 to +125 c. typical specs at 25 c parameter symbol test conditions min typ max units dc specifications input-side power supply voltage vddi 4.5 ? 5.5 v driver supply voltage vdda, vddb voltage between vdda and gnda, and vddb and gndb (see ?9. ordering guide? ) 6.5 ? 24 v input supply quiescent current iddi(q) SI8230/32/33/35/36 ? 2 3 ma si8231/34 ? 2 3 ma output supply quiescent current idda(q), iddb(q) current per channel ? ? 3.0 ma input supply active current iddi pwm freq = 500 khz ? 2.5 ? ma output supply active current iddo pwm freq = 500 khz ? 3.6 ? ma input pin leakage current ivia, ivib, ipwm ?10 ? +10 a dc input pin leakage current idisable ?10 ? +10 a dc logic high input threshold vih 2.0 ? ? v logic low input threshold vil ? ? 0.8 v input hysteresis vi hyst 400 450 ? mv logic high output voltage voah, vobh ioa, iob = ?1 ma (vdda /vddb) ? 0.04 ?? v logic low output voltage voal, vobl ioa, iob = 1 ma ? ? 0.04 v output short-circuit pulsed sink current ioa(scl), iob(scl) SI8230/1/2, figure 4 ? 0.5 ? a si8233/4/5/6, figure 4 ? 4.0 ? output short-circuit pulsed source current ioa(sch), iob(sch) SI8230/1/2, figure 5 ? 0.25 ? si8233/4/5/6, figure 5 ? 2.0 ? output sink resistance r on(sink) SI8230/1/2 ? 5.0 ? ? si8233/4/5/6 ? 1.0 ? output source resistance r on(source) SI8230/1/2 ? 15 ? si8233/4/5/6 ? 2.7 ? notes: 1. vdda = vddb = 12 v for 5, 8, and 10 v uvlo devices; vdda = vddb = 15 v for 12.5 v uvlo devices. 2. tdd is the minimum overlap time without tr iggering overlap protec tion (SI8230/1/3/4 only). 3. the largest rdt resistor that can be used is 220 k ? . free datasheet http:///
si823x rev. 0.3 7 vddi undervoltage threshold vddi uv+ vddi rising 3.60 4.0 4.45 v vddi undervoltage threshold vddi uv? vddi falling 3.30 3.70 4.15 v vddi lockout hysteresis vddi hys ?250?mv vdda, vddb undervoltage threshold vdda uv+ , vddb uv+ vdda, vddb rising 5 v threshold see figure 36 on page 25. 5.20 5.80 6.30 v 8 v threshold see figure 37 on page 25. 7.50 8.60 9.40 v 10 v threshold see figure 38 on page 25. 9.60 11.1 12.2 v 12.5 v threshold see figure 39 on page 25. 12.4 13.8 14.8 v vdda, vddb undervoltage threshold vdda uv? , vddb uv? vdda, vddb falling 5 v threshold see figure 36 on page 25. 4.90 5.52 6.0 v 8 v threshold see figure 37 on page 25. 7.20 8.10 8.70 v 10 v threshold see figure 38 on page 25. 9.40 10.1 10.9 v 12.5 v threshold see figure 39 on page 25. 11.6 12.8 13.8 v vdda, vddb lockout hysteresis vdda hys , vddb hys uvlo voltage = 5 v ? 280 ? mv vdda, vddb lockout hysteresis vdda hys , vddb hys uvlo voltage = 8 v ? 600 ? mv vdda, vddb lockout hysteresis vdda hys , vddb hys uvlo voltage = 10 v or 12.5 v ? 1000 ? mv ac specifications minimum pulse width ? 10 ? ns propagation delay t phl , t plh cl = 200 pf ? 30 60 ns pulse width distortion |t plh - t phl | pwd ? ? 5.60 ns minimum overlap time 2 tdd dt = vddi, no-connect ? 0.4 ? ns programmed dead time 3 dt figure 41, rdt = 100 k ? 900 ? ns figure 41, rdt = 6 k ? 70 ? ns output rise and fall time t r ,t f c l = 200 pf (SI8230/1/2) ? ? 12 ns c l = 200 pf (si8233/4/5/6) ? ? 20 ns table 1. electrical characteristics 1 (continued) 4.5 v < vddi < 5.5 v, vdda = vddb = 12 v or 15 v. ta = ?40 to +125 c. typical specs at 25 c parameter symbol test conditions min typ max units notes: 1. vdda = vddb = 12 v for 5, 8, and 10 v uvlo devices; vdda = vddb = 15 v for 12.5 v uvlo devices. 2. tdd is the minimum overlap time without tr iggering overlap protec tion (SI8230/1/3/4 only). 3. the largest rdt resistor that can be used is 220 k ? . free datasheet http:///
si823x 8 rev. 0.3 shutdown time from disable true t sd ??60 ns restart time from disable false t restart ??60 ns device start-up time t start time from vdd_ = vdd_uv+ to voa, vob = via, vib ?57s common mode transient immunity cmti via, vib, pwm = vddi or 0 v 30 50 ? kv/s table 1. electrical characteristics 1 (continued) 4.5 v < vddi < 5.5 v, vdda = vddb = 12 v or 15 v. ta = ?40 to +125 c. typical specs at 25 c parameter symbol test conditions min typ max units notes: 1. vdda = vddb = 12 v for 5, 8, and 10 v uvlo devices; vdda = vddb = 15 v for 12.5 v uvlo devices. 2. tdd is the minimum overlap time without tr iggering overlap protec tion (SI8230/1/3/4 only). 3. the largest rdt resistor that can be used is 220 k ? . free datasheet http:///
si823x rev. 0.3 9 2.1. test circuits figures 4 and 5 depict sink current and source current test circuits. figure 4. sink current test circuit figure 5. source current test circuit input 1 f 100 f 10 rsns 0.1 si823x 1 f cer 10 f el vdda = vddb = 15 v in_ out_ vss vdd schottky 50 ns 200 ns measure input waveform gnd vddi vddi (5 v) 5 v + _ input 1 f 100 f 10 rsns 0.1 si823x 1 f cer 10 f el vdda = vddb = 15 v in_ out_ vss vdd 50 ns 200 ns measure input waveform gnd vddi schottky vddi (5 v) 5 v + _ free datasheet http:///
si823x 10 rev. 0.3 table 2. absolute maximum ratings 1 parameter symbol min typ max units storage temperature 2 t stg ?65 ? +150 c ambient temperature under bias t a ?40 ? +125 c input-side supply voltage vddi ?0.6 ? 6.0 v driver-side supply voltage vdda, vddb ?0.6 ? 30 v voltage on any pin with respect to ground vin ?0.5 ? vdd + 0.5 v output drive current per channel i o ?? 10 ma lead solder temperature (10 sec.) ? ? 260 c maximum isolation (input to output) (1 sec) wb soic-16 ? ? 6500 v rms maximum isolation (output to output) (1 sec) wb soic-16 ? ? 2500 v rms maximum isolation (input to output) (1 sec) nb soic-16 ? ? 4250 v rms maximum isolation (output to output) (1 sec) nb soic-16 ? ? 2500 v rms maximum isolation (input to output) (1 sec) 14 ld lga without thermal pad ? ? 3850 v rms maximum isolation (output to output) (1 sec) 14 ld lga without thermal pad ?? 650 v rms maximum isolation (input to output) (1 sec) 14 ld lga with thermal pad ? ? 1850 v rms maximum isolation (output to output) (1 sec) 14 ld lga with thermal pad ?? 0 v rms notes: 1. permanent device damage may occur if the absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. vde certifies storage temperature from ?40 to 150 c. table 3. regulatory information* csa the si823x is certified under csa component acceptanc e notice 5a. for more details, see file 232873. vde the si823x is certified according to iec 60747-5-2. for more details, see file 5006301-4880-0001. ul the si823x is certified under ul15 77 component recognition program. for more details, see file e257455. *note: regulatory certifications apply to 1.5 kv rms rated devices which are production tested to 1.8 kv rms for 1 sec. regulatory certifications apply to 2.5 kv rms rated devices which are production tested to 3.0 kv rms for 1 sec. regulatory certifications apply to 3.75 kv rms rated devices which are production tested to 4.5 kv rms for 1 sec. regulatory certifications apply to 5.0 kv rms rated devices which are production tested to 6.0 kv rms for 1 sec. for more information, see "9.ordering guide" on page 37. free datasheet http:///
si823x rev. 0.3 11 table 4. insulation and safety-related specifications parameter symbol test condition value unit wbsoic-16 5kv rms nbsoic-16 wbsoic-16 2.5 kv rms 14 ld lga 2.5 kv rms 14 ld lga w/ pad 1.5 kv rms nominal air gap (clearance) 1 l(1o1) 8.0 4.01 3.5 1.75 mm nominal external tracking (creepage) 1 l(1o2) 8.0 4.01 3.5 1.75 mm minimum internal gap (internal clearance) 0.014 0.014 0.014 0.014 mm tracking resistance (comparative tracking index) cti din iec 60112/vde 0303 part 1 >175 >175 >175 >175 v resistance (input-output) 2 r io 10 12 10 12 10 12 10 12 ? capacitance (input-output) 2 c io f = 1 mhz 1.4 1.4 1.4 1.4 pf input capacitance 3 c i 4.0 4.0 4.0 4.0 pf notes: 1. the values in this table correspond to the nominal creepage a nd clearance values as detailed in ?10. package outline: 16-pin wide body soic? , ?12. package outline: narrow body soic? , ?14. pa ckage outline: 14 ld lga (5 x 5 mm)? , and ?16. package outline: 14 ld lga with thermal pad (5 x 5 mm)? . vde certifies the clearance and creepage limits as 4.7 mm minimum for the nb soic-16 and 8.5 mm minimu m for the wb soic-16 package. ul does not impose a clearance and creepage minimum for component level certif ications. csa certifies the clearance and creepage limits as 3.9 mm minimum for the nb soic 16 and 7.6 mm minimum for the wb soic-16 package. 2. to determine resistance and capacitance, the si823x is converted into a 2-terminal device . pins 1?8 (1-7, 14 ld lga) are shorted together to form the first terminal and pins 9? 16 (8-14, 14 ld lga) are shorted together to form the second terminal. the parameters are then measured between these two terminals. 3. measured from input pin to ground. table 5. iec 60664-1 (vde 0884 part 2) ratings parameter test conditions specification wb soic-16 nb soic-16 14 ld lga 14 ld lga w/ pad basic isolation group material group iiia iiia iiia iiia installation classification rated mains voltages < 150 v rms i-iv i-iv i-iv i-iv rated mains voltages < 300 v rms i-iv i-iii i-iii i-iii rated mains voltages < 400 v rms i-iiii-iii-iii-ii rated mains voltages < 600 v rms i-iii i-ii i-ii i-i free datasheet http:///
si823x 12 rev. 0.3 table 6. iec 60747-5-2 insulation characteristics* parameter symbol test condition characteristic unit wb soic-16 nb soic-16 14 ld lga 14 ld lga w/ pad maximum working insulation voltage v iorm 891 560 373 v peak input to output test voltage v pr method a after environmen- tal tests subgroup 1 (v iorm x1.6=v pr , t m = 60 sec, partial discharge < 5 pc) 1590 896 597 v peak method b1 (v iorm x1.875=v pr , 100% production test, t m = 1 sec, partial discharge < 5 pc) 1375 1050 700 after input and/or safety test subgroup 2/3 (v iorm x1.2=v pr , t m = 60 sec, partial discharge < 5 pc) 1018 672 448 highest allowable overvolt- age (transient overvoltage, t tr = 10 sec) v tr 6000 4000 2650 v peak pollution degree (din vde 0110, table 1) 222 insulation resistance at t s , v io =500v r s >10 9 >10 9 >10 9 ? *note: the si823x is suitable for basic electrical isolation within the safety limit data. maintenance of the safety data is ensured by protective circuits. the si823x prov ides a climate classification of 40/125/21. free datasheet http:///
si823x rev. 0.3 13 table 7. iec safety limiting values 1 parameter symbol test condition wb soic-16 nb soic-16 14 ld lga 14 ld lga w/ pad unit case temperature t s 150 150 150 150 c safety input current i s ? ja = 100 c/w (wb soic-16), 105 c/w (nb soic-16, 14 ld lga), 50 c/w (14 ld lga w/ pad) v ddi =5.5v, v dda =v ddb =24v, t j = 150 c, t a =25c 50 50 50 100 ma device power dissipation 2 p d 1.2 1.2 1.2 1.2 w notes: 1. maximum value allowed in the event of a failure. refer to the thermal derating curve in figure 6. 2. the si823x is tested with v ddi = 5.5 v, v dda =v ddb =24v, t j =150oc, c l = 100 pf, input 2 mhz 50% duty cycle square wave. free datasheet http:///
si823x 14 rev. 0.3 figure 6. wb soic-16, nb soic-16, 14 ld lga thermal derating curve, dependence of safety limiting values with case temperature per din en 60747-5-2 figure 7. 14 ld lga with pad thermal derating curve, dependence of safety limiting values with case temperature per din en 60747-5-2 table 8. thermal characteristics parameter symbol wb soic-16 nb soic-16 14 ld lga 14 ld lga w/ pad unit ic junction-to-air thermal resis- tance ? ja 100 105 105 50 c/w 0 200 150 100 50 60 40 20 0 case temperature (oc) safety-limiting current (ma) vddi = 5.5 v vdda, vddb = 24 v 10 30 50 0 200 150 100 50 120 80 40 0 case temperature (oc) safety-limiting current (ma) 20 60 100 vddi = 5.5 v vdda, vddb = 24 v free datasheet http:///
si823x rev. 0.3 15 2.2. theory of operation the operation of an si823x channel is analogous to that of an opto coupler and gate driver, except an rf carrier is modulated instead of light. this simple architecture provid es a robust isolated data path and requires no special considerations or initialization at start-up. a simplified block diagram for a single si823x channel is shown in figure 8. figure 8. simplified channel diagram a channel consists of an rf transmitter and rf receiver separated by a semiconductor-based isolation barrier. referring to the transmitter, input a modulates the carrier provided by an rf oscillator using on/off keying. the receiver contains a demodulator that decodes the input state according to its rf energy content and applies the result to output b via the output driv er. this rf on/off keying scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consum ption, and better immunity to magnetic fields. see figure 9 for more details. figure 9. modulation scheme rf oscillator modulator demodulator a b semiconductor- based isolation barrier transmitter receiver dead time control 0.5 to 4 a peak gnd v dd driver input signal output signal modulation signal free datasheet http:///
si823x 16 rev. 0.3 3. typical operating characteristics (0.5 amp) the typical performance characteristics depicted in figures 10 through 21 are for information purposes only. refer to table 1 on page 6 for actual specification limits. figure 10. rise/fall time vs. supply voltage figure 11. propagation delay vs. supply voltage figure 12. supply current vs. supply voltage figure 13. supply current vs. supply voltage figure 14. supply current vs. temperature figure 15. rise/fall time vs. load 0 2 4 6 8 10 9 1215182124 rise/fall time (ns) vdda supply (v) vdd=12v, 25 c c l = 100 pf tfall trise 10 15 20 25 30 9 1215182124 propagation delay (ns) vdda supply (v) h-l l-h vdd=12v, 25 c c l = 100 pf 1 1.5 2 2.5 3 3.5 4 9 141924 vdda supply current (ma) vdda supply voltage (v) duty cycle = 50% c l = 0 pf 1 channel switching 1mhz 500khz 100khz 50 khz 0 1 2 3 4 5 6 7 9 141924 vdda supply current (ma) vdda supply voltage (v) duty cycle = 50% c l = 100 pf 1 channel switching 1mhz 500khz 100khz 50 khz 1 2 3 4 5 -50 0 50 100 supply current (ma) temperature (c) vdda = 15v, f = 250khz, c l = 0 pf duty cycle = 50% 2 channels switching 0 5 10 15 20 25 30 35 40 0.0 0.5 1.0 1.5 2.0 rise/fall time (ns) load (nf) vdd=12v, 25 c tfall trise free datasheet http:///
si823x rev. 0.3 17 figure 16. propagation delay vs. load figure 17. propagation delay vs. temperature figure 18. output sink current vs. supply voltage figure 19. output source current vs. supply voltage figure 20. output sink current vs. temperature figure 21. output source current vs. temperature 10 15 20 25 30 35 40 45 50 0.0 0.5 1.0 1.5 2.0 propagation delay (ns) load (nf) vdd=12v, 25 c h-l l-h 10 15 20 25 30 -40 -20 0 20 40 60 80 100 120 propagation delay (ns) temperature ( c) vdd=12v, load = 200pf h-l l-h 4 5 6 7 8 9 10 12 14 16 18 20 22 24 sink current (a) supply voltage (v) vdd=12v, vout=5v 2 2.25 2.5 2.75 3 3.25 3.5 3.75 4 10 15 20 25 source current (a) supply voltage (v) vdd=12v, vout=vdd-5v 4 4.25 4.5 4.75 5 5.25 5.5 5.75 6 6.25 6.5 6.75 7 -40 -10 20 50 80 110 sink current (a) temperature ( c) vdd=12v, vout=5v 2 2.25 2.5 2.75 3 3.25 3.5 -40 -10 20 50 80 110 source current (a) temperature ( c) vdd=12v, vout=vdd-5v free datasheet http:///
si823x 18 rev. 0.3 4. typical operating characteristics (4.0 amp) the typical performance characteristics depicted in figures 22 through 33 are for information purposes only. refer to table 1 on page 6 for actual specification limits. figure 22. rise/fall time vs. supply voltage figure 23. propagation delay vs. supply voltage figure 24. supply current vs. supply voltage figure 25. supply current vs. supply voltage figure 26. supply current vs. temperature figure 27. rise/fall time vs. load 0 2 4 6 8 10 9 1215182124 rise/fall time (ns) vdda supply (v) vdd=12v, 25 c c l = 100 pf tfall trise 10 15 20 25 30 9 1215182124 propagation delay (ns) vdda supply (v) h-l l-h vdd=12v, 25 c c l = 100 pf 0 2 4 6 8 10 12 14 9141924 vdda supply current (ma) vdda supply voltage (v) duty cycle = 50% c l = 0 pf 1 channel switching 1mhz 500khz 100khz 50 khz 0 2 4 6 8 10 12 14 9 141924 vdda supply current (ma) vdda supply voltage (v) duty cycle = 50% c l = 100 pf 1 channel switching 1mhz 500khz 100khz 50 khz 0 2 4 6 8 10 -50 0 50 100 supply current (ma) temperature (c) vdda = 15v, f = 250khz, c l = 0 pf duty cycle = 50% 2 channels switching 0 5 10 15 20 25 30 35 40 012345678910 rise/fall time (ns) load (nf) vdd=12v, 25 c tfall trise free datasheet http:///
si823x rev. 0.3 19 figure 28. propagation delay vs. load figure 29. propagation delay vs. temperature figure 30. output sink current vs. supply voltage figure 31. output source current vs. supply voltage figure 32. output sink current vs. temperature figure 33. output source current vs. temperature 10 15 20 25 30 35 40 45 50 012345678910 propagation delay (ns) load (nf) vdd=12v, 25 c h-l l-h 10 15 20 25 30 -40 -20 0 20 40 60 80 100 120 propagation delay (ns) temperature ( c) vdd=12v, load = 200pf h-l l-h 4 5 6 7 8 9 10 12 14 16 18 20 22 24 sink current (a) supply voltage (v) vdd=12v, vout=5v 2 2.25 2.5 2.75 3 3.25 3.5 3.75 4 10 15 20 25 source current (a) supply voltage (v) vdd=12v, vout=vdd-5v 4 4.25 4.5 4.75 5 5.25 5.5 5.75 6 6.25 6.5 6.75 7 -40 -10 20 50 80 110 sink current (a) temperature ( c) vdd=12v, vout=5v 2 2.25 2.5 2.75 3 3.25 3.5 -40 -10 20 50 80 110 source current (a) temperature ( c) vdd=12v, vout=vdd-5v free datasheet http:///
si823x 20 rev. 0.3 5. application information the si823x family of isolated drivers consists of high-side, low-side, and dual driver configurations. 5.1. products table 9 shows the configuration and functional overview for each product in this family. 5.2. device behavior table 10 contains truth tables for the si 8230/3, si8231 /4, and si8232/ 5/6 families. table 9. si823x family overview part number configuration overlap protection programmable dead time inputs peak output current (a) SI8230 high-side/low-side ?? via, vib 0.5 si8231 high-side/low-side ?? pwm 0.5 si8232 dual driver ? ? via, vib 0.5 si8233 high-side/low-side ?? via, vib 4.0 si8234 high-side/low-side ?? pwm 4.0 si8235/6 dual driver ? ? via, vib 4.0 table 10. si823x family truth table* SI8230/3 (high-side/low-side) truth table inputs vddi state disable output notes via vib voa vob llpoweredl ll output transition occurs after internal dead time expires. lhpoweredl lh output transition occurs after internal dead time expires. hlpoweredl hl output transition occurs after internal dead time expires. hhpoweredl l l invalid state. output transition occurs after internal dead time expires. x x unpowered x l l output returns to input state within 7 s of vddi power restoration. x x powered h l l device is disabled. si8231/4 (pwm input high-si de/low-side) truth table pwm input vddi state disable output notes voa vob h powered l h l output transition occurs after internal dead time expires. l powered l l h output transition occurs after internal dead time expires. x unpowered x l l output returns to input state within 7 s of vddi power restoration. x powered h l l device is disabled. *note: this truth table assumes vdda and vddb are powered. if vdda or vddb power is lost, the respective output state (voa or vob) is undetermined. free datasheet http:///
si823x rev. 0.3 21 si8232/5/6 (dual driver) truth table inputs vddi state disable output notes via vib voa vob llpoweredl ll output transition occurs immediately (no internal dead time). lhpoweredl lh output transition occurs immediately (no internal dead time). hlpoweredl hl output transition occurs immediately (no internal dead time). hhpoweredl hh output transition occurs immediately (no internal dead time). x x unpowered x l l output returns to input state within 7 s of vddi power restoration. x x powered h l l device is disabled. table 10. si823x family truth table* (continued) *note: this truth table assumes vdda and vddb are powered. if vdda or vddb power is lost, the respective output state (voa or vob) is undetermined. free datasheet http:///
si823x 22 rev. 0.3 5.3. power supply connections isolation requirements mandate individual supplies fo r vddi, vdda, and vddb. the decoupling caps for these supplies must be placed as close to the vdd and gnd pi ns of the si823x as possible. the optimum values for these capacitors depend on load current and the distance between the chip and the regulator that powers it. low effective series resistance (esr) capacitors, such as tantalum, are recommended. 5.4. power dissipation considerations proper system design must assure that the si823x operates within safe therma l limits across the entire load range. the si823x total power dissipation is the sum of the power dissipated by bias supply current, internal switching losses, and power delivered to the load. equation 1 show s total si823x power dissipation. in a non-overlapping system, such as a high-side/low-side driver, n = 1. for a dual driver with each driver having an independent load, n can have a maximum value of 2, corresponding to a 100% overlap between the two outputs. equation 1. the maximum power dissipation allowable for the si823x is a function of the package thermal resistance, ambient temperature, and maximum allowable juncti on temperature, as shown in equation 2: equation 2. substituting values fo r pdmax tjmax, ta, and ? ja into equation 2 results in a maximum allowable total power dissipation of 1.1 w. maximum allowable load is found by substituting this limit and the appropriate datasheet values from table 1 on page 6 into equation 1 and si mplifying. the result is equation 3 (0.5 a driver) and equation 4 (4.0 a driver), both of which assume vddi = 5 v and vdda = vddb = 18 v. equation 3. equation 4. p d v ddi i ddi 2v ddo i qout c int v ddo 2 f + ?? 2n c l v ddo 2 f ?? ++ where: p d is the total si823x device power dissipation (w) i ddi is the input-side maximum bias current (3 ma) i qout is the driver die maximum bias current (2.5 ma) c int is the internal parasitic capacitance (75 pf for the 0.5 a driver and 370 pf for the 4.0 a driver) v ddi is the input-side vdd supply voltage (4.5 to 5.5 v) v ddo is the driver-side supply voltage (10 to 24 v) f is the switching frequency (hz) n is the overlap constant (max value = 2) = p dmax t jmax t a ? ? ja --------------------------- where: p dmax = maximum si823x power dissipation (w) t jmax = si823x maximum junction temperature (145 c) t a = ambient temperature (c) ? ja = si823x junction-to-air thermal resistance (105 c/w) f = si823x switching frequency (hz) ? c l(max) 1.4 10 3 ? ? f -------------------------- 7.5 ? 10 11 ? ? = c l(max) 1.4 10 3 ? ? f -------------------------- 3.7 ? 10 10 ? ? = free datasheet http:///
si823x rev. 0.3 23 equation 1 and equation 2 are graphed in figure 34 where the points along the load line represent the package dissipation-limited value of cl for the corresponding switching frequency. figure 34. max load vs. switching frequency 0 2,000 4,000 6,000 8,000 10,000 12,000 14,000 16,000 100 150 200 250 300 350 400 450 500 550 600 650 700 frequency (khz) max load (pf) 0.5a driver (pf) 4a driver (pf) free datasheet http:///
si823x 24 rev. 0.3 5.5. layout considerations it is most important to minimize ringing in the drive path and noise on the si823x vdd lines. care must be taken to minimize parasitic inductance in these pa ths by locating the si823x as close to the device it is driving as possible. in addition, the vdd supply and ground trace paths must be kept short. for this re ason, the use of power and ground planes is highly recommended. a split ground plane system having separate ground and vdd planes for power devices and small signal components provides the best overall noise performance. 5.6. device operation device behavior during start-up, normal operation and shutdown is shown in figure 35, where uvlo+ and uvlo- are the positive-going and negative-going thresholds respectively. note that outputs voa and vob default low when input side power su pply (vddi) is not present. 5.6.1. device startup outputs voa and vob are held low during power-up un til vdd is above the uvlo threshold for time period tstart. following this, the outputs follow the states of inputs via and vib. 5.6.2. under voltage lockout under voltage lockout (uvlo) is provided to prevent erroneous operation during device startup and shutdown or when vdd is below its specified operating circuits range. the input (control) side, driver a and driver b, each have their own under voltage lockout monitors. the si823x input side enters uvlo when vddi < vddi uv? , and exits uvlo when vddi > vddi uv+ . the driver outputs, voa and vob, remain low when the input side of the si823x is in uvlo and their respective vdd supply (vdda, vddb) is within toler ance. each driver output can enter or ex it uvlo independently. for example, voa unconditionally enters uvlo when vdda falls below vdda uv? and exits uvlo when vdda rises above vdda uv+ . figure 35. device behavior during normal operation and shutdown via voa disable vddi uvlo- vdda tstart tstart tstart tsd trestart tphl tplh uvlo+ uvlo- uvlo+ tsd vdd hys vdd hys free datasheet http:///
si823x rev. 0.3 25 5.6.3. under voltage lockout (uvlo) the uvlo circuit unconditionally drives vo low when vdd is below the lockout threshol d. referring to figures 36 through 39, upon power up, the si823x is main tained in uvlo unt il vdd rises above vdd uv+ . during power down, the si823x enters uvlo when vdd falls below th e uvlo threshold plus hy steresis (i.e., vdd < vdd uv+ ? vdd hys ). figure 36. si823x uvlo response (5 v) figure 37. si823x uvlo response (8 v) figure 38. si823x uvlo response (10 v) figure 39. si823x uvlo response (12.5 v) 3.5 10.5 v dduv+ (typ) output voltage (v o ) 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 supply voltage (v dd - v ss ) (v) 6.0 10.5 v dduv+ (typ) output voltage (v o ) 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 supply voltage (v dd - v ss ) (v) 8.5 10.5 v dduv+ (typ) output voltage (v o ) 9.0 9.5 10.0 10.5 11.0 11.5 12.0 12.5 supply voltage (v dd - v ss ) (v) 11.3 10.5 v dduv+ (typ) output voltage (v o ) 11.8 12.3 12.8 13.3 13.8 14.3 14.8 15.3 supply voltage (v dd - v ss ) (v) free datasheet http:///
si823x 26 rev. 0.3 5.6.4. control inputs via, vib, and pwm inputs are high-true, ttl level-compatible logic inputs. a logic high signal on via or vib causes the corresponding output to go high. for pwm input versions (si8231/4), voa is high and vob is low when the pwm input is high, and voa is low and vob is high when the pwm input is low. 5.6.5. disable input when brought high, the disable input un conditionally drives voa and vob lo w regardless of th e states of via and vib. device operation term inates within tsd after disable = v ih and resumes within trestart after disable = v il . the disable input has no effect if vddi is below its uvlo level (i.e. voa, vob remain low). 5.7. programmable dead time and overlap protection all high-side/low-side drivers (si823 0/1/3/4) include programmable overlap protection to prevent outputs voa and vob from being high at the same time . these devices also include programm able dead time, which adds a user- programmable delay between transitions of voa and vob (f igure 26.a). when enabled, dead time is present on all transitions, even after overlap recovery (figure 26.b). the amount of dead time delay (dt) is programmed by a single resistor (rdt) connected from the dt input to ground per equation 5. note that the dead time pin can be tied to vddi or left floating to provi de a nominal dead time at approximately 400 ps. equation 5. the device driving via and vib should provide a minimum dead time of tdd to avoid activating overlap protection. input/output timing wa veforms for the two-input drivers are shown in figure 40, and dead time waveforms are shown in figure 41. figure 40. input / output waveforms for high-side / low-side two-input drivers dt 10 rdt where: ? dt dead time (ns) and rdt dead time programming resistor (k ?? = = ? via vib voa vob ` a b c d e f g h i ref description a normal operation: vi a high, vib low. b normal operation: vi b high, via low. c contention: via = vib = high. d recovery from contention: via transitions low. e normal operation: via = vib = low. f normal operation: vi a high, vib low. g contention: via = vib = high. h recovery from contention: vib transitions low. i normal operation: vib transitions high. free datasheet http:///
si823x rev. 0.3 27 figure 41. dead time waveforms for high-side/low-side two-input drivers via vib voa vob dt dt 10% 10% 90% 90% 50% vob a. typical dead time operation via voa vob dt dt vib dt dt overlap overlap b. dead time operation during overlap free datasheet http:///
si823x 28 rev. 0.3 6. rf radiated emissions the si823x family uses a rf carrier frequency of app roximately 700 mhz. this re sults in a small amount of radiated emissions at this frequency and its harmonics. the radi ation is not from the ic but, rather, is due to a small amount of rf energy driving the isolated grou nd planes which can act as a dipole antenna. the unshielded SI8230 evaluation board passes fcc class b (part 15) requirements. table 11 shows measured emissions compared to fcc requirements. note that the da ta reflects worst-case conditions where all inputs are tied to logic 1 and the rf tr ansmitters are fully active. radiated emissions can be reduced if the circuit board is enclosed in a shielded enclosure or if the pcb is a less efficient antenna. 6.1. rf, magnetic, and co mmon mode transient immunity the si823x families have very high common mode transient immunity while transmitting data. this is typically measured by applying a square pulse with very fast rise/fall times between the isolated grounds. measurements show no failures at 30 kv/s (minimum). during a high surge event, the output may glitch low for up to 20?30 ns, but the output corrects immediately after the surge event. the si823x families pass the industri al requirements of cispr24 for rf immunity of 10 v/m using an unshielded evaluation board. as shown in figure 20, the isolated ground planes form a parasitic dipole antenna. the pcb should be laid-out to not act as an ef ficient antenna for the rf frequency of interest. rf susceptibility is also significantly reduced when the end system is hous ed in a metal enclosure, or otherwise shielded. the si823x digital isolator can be us ed in close proximity to large moto rs and various other magnetic-field producing equipment. in theory, data transmission errors can occur if the magnetic field is too large and the field is too close to the isolator. however, in actual use, the si823x devices provide extremely high immunity to external magnetic fields and have been indepe ndently evaluated to withstand magn etic fields of at least 1000 a/m according to the iec 61000-4-8 and iec 61000-4-9 specifications. figure 42. dipole antenna table 11. radiated emissions frequency (mhz) measured (dbv/m) fcc spec (dbv/m) compared to spec (db) 712 29 37 ?8 1424 39 54 ?15 2136 42 54 ?12 2848 43 54 ?11 4272 44 54 ?10 4984 44 54 ?10 5696 44 54 ?10 isolator gnd1 gnd2 dipole antenna free datasheet http:///
si823x rev. 0.3 29 7. applications the following examples illustrate typical circuit configurations using the si823x. 7.1. high-side / low-side driver figure 43a shows the SI8230/3 controlled using the via an d vib input signals, and figure 43b shows the si8231/4 controlled by a single pwm signal. figure 43. si823x in half-bridge application for both cases, d1 and cb form a conventional bootstrap circuit that allows voa to operate as a high-side driver for q1, which has a maximum drain voltage of 1500 v. vob is connected as a conventional low-side driver. note that the input side of the si823x requires vdd in the r ange of 4.5 to 5.5 v, while th e vdda and vddb output side supplies must be between 6.5 and 24 v wit h respect to their respective grou nds. the boot-stra p start up time will depend on the cb cap chosen. vdd2 is usually the same as vddb. also note that the bypass capacitors on the si823x should be located as close to the chip as poss ible. moreover, it is recommended that 0.1 and 10 f bypass capacitors be used to reduce high frequency noise and maximize performance. SI8230/3 cb 1500 v max gndi vddi via vdda voa gnda vob vddi vddb gndb disable vdd2 dt rdt controller vib c1 1uf out1 out2 i/o q1 q2 d1 vddb c3 10uf c2 1 f si8231/4 cb gndi vddi pwm vdda voa gnda vob vddi vddb gndb disable dt rdt controller c1 1uf pwmout i/o q1 q2 d1 vddb c3 10uf ab vdd2 c2 1 f 1500 v max free datasheet http:///
si823x 30 rev. 0.3 7.2. dual driver figure 44 shows the si823x configured as a dual driver. note that the drain voltages of q1 and q2 can be referenced to a common ground or to different grounds with as much as 1500 v dc between them. figure 44. si8235 in a dual driver application 7.3. dual driver with the rmally enhanced package (si8236) the thermal pad of the si8236 must be connected to a he at spreader to lower thermal resistance. generally, the larger the thermal shield?s area, the lower the thermal re sistance. it is recommended that a thermal vias also be used to add mass to the shield. vias generally have much more mass than the shield alone and consume less space, thus reducing thermal resistance more effectively. while the heat spreader is not generally a circuit ground, it is a good reference plane for the si8236 and is also useful as a shield layer for emi reduction. with a 10mm 2 thermal plane on the outer layers (including 20 thermal vias), the thermal impedance of the si8236 was measured at 50 c/w. this is a significant improvem ent over the si835 which does not include a thermal pad. the si8235?s thermal resistance was measured at 105 c /w. si8235/6 gndi vddi via vdda voa gnda vob vddi vddb gndb disable controller vib ph1 ph2 i/o q1 q2 vdda vddb c3 10 f c2 10 f c1 10 f free datasheet http:///
si823x rev. 0.3 31 8. pin descriptions table 12. SI8230/3 two-input hs/ls isolated driver (soic-16) pin name description 1 via non-inverting logic in put terminal for driver a. 2 vib non-inverting logic in put terminal for driver b. 3 vddi input-side power supply terminal; connect to a source of 4.5 to 5.5 v. 4 gndi input-side ground terminal. 5 disable device disable. when high, this input uncond itionally drives outputs voa, vob low. it is strongly recommended that this input be connect ed to external logic level to avoid erroneous operation due to capacitive noise coupling. 6 dt dead time programming input. the value of the resistor connected from dt to ground sets the dead time between output transitions of voa and vob. defaults to 1 ns dead time when con- nected to vddi or left open (see "5.7.progr ammable dead time and overlap protection" on page 26). 7 nc no connection. 8 vddi input-side power supply terminal; connect to a source of 4.5 to 5.5 v. 9 gndb ground terminal for driver b. 10 vob driver b output (low-side driver). 11 vddb driver b power supply voltage terminal; connect to a source of 6.5 to 24 v. 12 nc no connection. 13 nc no connection. 14 gnda ground terminal for driver a. 15 voa driver a output (high-side driver). 16 vdda driver a power supply voltage terminal; connect to a source of 6.5 to 24 v. via vib vddi gndi disable dt nc vddi vdda voa gnda nc nc vddb vob gndb SI8230 si8233 soic-16 (wide) via vib vddi gndi disable dt nc vddi vdda voa gnda nc nc vddb vob gndb SI8230 si8233 soic-16 (narrow) 1 2 3 4 5 6 7 8 9 12 11 10 13 14 15 16 1 2 3 4 5 6 7 8 9 12 11 10 13 14 15 16 free datasheet http:///
si823x 32 rev. 0.3 table 13. si8231/4 pwm input hs/ls isolated driver (soic-16) pin name description 1 pwm pwm input. 2 nc no connection. 3 vddi input-side power supply terminal; connect to a source of 4.5 to 5.5 v. 4 gndi input-side ground terminal. 5 disable device disable. when high, this input uncond itionally drives outputs voa, vob low. it is strongly recommended that this input be connect ed to external logic level to avoid erroneous operation due to capacitive noise coupling. 6 dt dead time programming input. the value of the resistor connected from dt to ground sets the dead time between output transitions of voa and vob. defaults to 1 ns dead time when con- nected to vddi or left open (see "5.7.progr ammable dead time and overlap protection" on page 26). 7 nc no connection. 8 vddi input-side power supply terminal; connect to a source of 4.5 to 5.5 v. 9 gndb ground terminal for vob driver output. 10 vob driver b output (low-side driver). 11 vddb driver b power supply voltage terminal; connect to a source of 6.5 to 24 v. 12 nc no connection. 13 nc no connection. 14 gnda ground terminal for driver a. 15 voa driver a output (high-side driver). 16 vdda driver a power supply voltage terminal; connect to a source of 6.5 to 24 v. pwm nc vddi gndi disable dt nc vddi vdda voa gnda nc nc vddb vob gndb si8231 si8234 soic-16 (wide) pwm nc vddi gndi disable dt nc vddi vdda voa gnda nc nc vddb vob gndb si8231 si8234 soic-16 (narrow) 1 2 3 4 5 6 7 8 9 12 11 10 13 14 15 16 1 2 3 4 5 6 7 8 9 12 11 10 13 14 15 16 free datasheet http:///
si823x rev. 0.3 33 table 14. si8232/5 dual isolated driver (soic-16) pin name description 1 via non-inverting logic inpu t terminal for driver a. 2 vib non-inverting logic inpu t terminal for driver b. 3 vddi input-side power supply terminal; co nnect to a source of 4.5 to 5.5 v. 4 gndi input-side ground terminal. 5 disable device disable. w hen high, this inpu t unconditionally drives ou tputs voa, vob low. it is strongly recommended that this input be connect ed to external logic level to avoid erroneous operation due to capacitive noise coupling. 6 nc no connection. 7 nc no connection. 8 vddi input-side power supply terminal; co nnect to a source of 4.5 to 5.5 v. 9 gndb ground terminal for vob driver output. 10 vob driver b output. 11 vddb driver output vob power supply voltage terminal; connect to a source of 6.5 to 24 v. 12 nc no connection. 13 nc no connection. 14 gnda ground terminal for driver a. 15 voa driver b output. 16 vdda driver a power supply voltage terminal; connect to a source of 6.5 to 24 v. via nc vddi gndi disable nc vib vddi vdda voa gnda nc nc vddb vob gndb si8232 si8235 soic-16 (wide) via vib vddi gndi disable nc nc vddi vdda voa gnda nc nc vddb vob gndb si8232 si8235 soic-16 (narrow) 1 2 3 4 5 6 7 8 9 12 11 10 13 14 15 16 1 2 3 4 5 6 7 8 9 12 11 10 13 14 15 16 free datasheet http:///
si823x 34 rev. 0.3 table 15. si8233 two-input hs/ls isolated driver (14 ld lga) pin name description gndi 1 input-side ground terminal. via 2 non-inverting logic in put terminal for driver a. vib 3 non-inverting logic in put terminal for driver b. vddi 4 input-side power supply terminal; connect to a source of 4.5 to 5.5 v. disable 5 device disable. when high, this input unconditionally dr ives outputs voa, vob low. it is strongly recommended that this input be connected to external logic level to avoid erroneous operation due to capacitive noise coupling. dt 6 dead time programming input. the value of the resistor connected from dt to ground sets the dead time between output transiti ons of voa and vob. defaults to 1 ns dead time when connected to vddi or left open (see"5.7.programmable dead time and overlap protection" on page 26). vddi 7 input-side power supply terminal; connect to a source of 4.5 to 5.5 v. gndb 8 ground terminal for driver b. vob 9 driver b output (low-side driver). vddb 10 driver b power supply voltage terminal; connect to a source of 6.5 to 24 v. nc 11 no connection. gnda 12 ground terminal for driver a. voa 13 driver a output (high-side driver). vdda 14 driver a power supply voltage terminal; connect to a source of 6.5 to 24 v. lga-14 (5 x 5 mm) gndi via vib vddi disable dt vddi vdda voa gnda nc vddb vob gndb si8233 1 2 3 4 5 6 7 14 13 12 11 10 7 8 free datasheet http:///
si823x rev. 0.3 35 table 16. si8234 pwm input hs/ls isolated driver (14 ld lga) pin name description gndi 1 input-side ground terminal. pwm 2 pwm input. nc 3 no connection. vddi 4 input-side power supply terminal; connect to a source of 4.5 to 5.5 v. disable 5 device disable. when high, this input unconditionally dr ives outputs voa, vob low. it is strongly recommended that this input be connected to external logic level to avoid erroneous operation due to capacitive noise coupling. dt 6 dead time programming input. the value of the resistor connected from dt to ground sets the dead time between output transiti ons of voa and vob. defaults to 1 ns dead time when connected to vddi or left open (see "5.7.programmable dead time and overlap protection" on page 26). vddi 7 input-side power supply terminal; connect to a source of 4.5 to 5.5 v. gndb 8 ground terminal for driver b. vob 9 driver b output (low-side driver). vddb 10 driver b power supply voltage terminal; connect to a source of 6.5 to 24 v. nc 11 no connection. gnda 12 ground terminal for driver a. voa 13 driver a output (high-side driver). vdda 14 driver a power supply voltage terminal; connect to a source of 6.5 to 24 v. lga-14 (5 x 5 mm) gndi pwm nc vddi disable dt vddi vdda voa gnda nc vddb vob gndb si8234 1 2 3 4 5 6 7 14 13 12 11 10 7 8 free datasheet http:///
si823x 36 rev. 0.3 table 17. si8235/6 dual isolated driver (14 ld lga) pin name description gndi 1 input-side ground terminal. via 2 non-inverting logic in put terminal for driver a. vib 3 non-inverting logic in put terminal for driver b. vddi 4 input-side power supply terminal; connect to a source of 4.5 to 5.5 v. disable 5 device disable. when high, this input unconditionally dr ives outputs voa, vob low. it is strongly recommended that this input be connected to external logic level to avoid erroneous operation due to capacitive noise coupling. nc 6 no connection. vddi 7 input-side power supply terminal; connect to a source of 4.5 to 5.5 v. gndb 8 ground terminal for driver b. vob 9 driver b output (low-side driver). vddb 10 driver b power supply voltage terminal; connect to a source of 6.5 to 24 v. nc 11 no connection. gnda 12 ground terminal for driver a. voa 13 driver a output (high-side driver). vdda 14 driver a power supply voltage terminal; connect to a source of 6.5 to 24 v. lga-14 (5 x 5 mm) gndi via vib vddi disable nc vddi vdda voa gnda nc vddb vob gndb si8235 si8236 1 2 3 4 5 6 7 14 13 12 11 10 7 8 free datasheet http:///
si823x rev. 0.3 37 9. ordering guide the ordering part number (opn) naming convention is de scribed in figure 45. the currently available opns are listed in table 18. the part number convention is not intended to imply that all possible device configuration options and their corresponding ordering part numbers (opn) will be available or ar e included in the or dering guide table. however, if there is a specific device configuration of interest that is currently not listed in the ordering guide table, contact your local silicon labs sales representative, or go to the silicon labs technical support web page at https://www.silabs.com/support/pa ges/contacttechnicalsupport.aspx and register to submit a request for your specific device configurat ion and opn. ordering part number options for 10 v an d 12.5 v uvlo will be made available only by request. figure 45. isodriver opn naming convention note: uvlo = under voltage lock out for vdda, vddb. si823yuv-r-tpn isodriver product peak output current (0,1,2=0.5a, 3,4,5=4a) uvlo* level (a=5v, b=8v, c=10v, d=12.5v) insulation rating (a=1.5kv,b=2.5kv,c=3.75kv,d=5kv) product revision temp range (i=-40 to +125c) package type (s=soic, m=lga) package extension (1=narrow body) free datasheet http:///
si823x 38 rev. 0.3 table 18. ordering part numbers ordering part number (opn) inputs configuration peak current uvlo voltage isolation rating temperature range package type legacy ordering part number (opn) 2.5 kv only wide body (wb) package options SI8230bb-b-is via, vib high side/ low side 0.5a 8v 2.5 kvrms ?40 to +125 c soic-16 wide body SI8230-a-is si8231bb-b-is pwm high side/ low side si8231-a-is si8232bb-b-is via,vib d ual driver si8232-a-is si8233bb-c-is via,vib high side/ low side 4.0a 8v si8233-b-is si8234bb-c-is pwm high side/ low side si8234-b-is si8235bb-c-is via,vib d ual driver si8235-b-is narrow body (nb) package options SI8230bb-b-is1 via,vib high side/ low side 0.5a 8v 2.5 kvrms ?40 to +125 c soic-16 narrow body n/a si8231bb-b-is1 pwm high side/ low side si8232bb-b-is1 via,vib dual driver si8233bb-c-is1 via,vib high side/ low side 4.0a 8v si8234bb-c-is1 pwm high side/ low side si8235bb-c-is1 via,vib dual driver note: all packages are rohs-compliant. moisture sensitivity level is msl3 for wide-body soic -16 and 14-ld lga packages and msl2a for narrow-body soic-16 packages with peak reflow temperatures of 260 c according to the jedec industry standard classifications and peak solder temperatures. free datasheet http:///
si823x rev. 0.3 39 lga package options si8233bb-c-im via,vib high side/ low side 4.0 a 8v 2.5 kvrms ?40 to +125 c lga-14 5x5 mm si8233-b-im si8234bb-c-im pwm high side/ low side si8234-b-im si8235bb-c-im via,vib dual driver si8235-b-im si8235ab-c-im via,vi b dual driver 5 v n/a si8236ba-c-im via, vib dual driver 8 v 1.5 kvrms lga-14 5x5 mm with ther- mal pad si8236-b-im si8236aa-c-im via,vib dual driver 5 v 5 kv ordering options SI8230bd-b-is via, vib high side/ low side 0.5 a 8 v 5.0 kvrms ?40 to +125 c soic-16 wide body n/a si8231bd-b-is pwm high side/ low side si8232bd-b-is via, vib dual driver si8233bd-c-is via, vib high side/ low side 4.0 a si8234bd-c-is pwm high side/ low side si8235bd-c-is via, vib dual driver table 18. ordering part numbers (continued) ordering part number (opn) inputs configuration peak current uvlo voltage isolation rating temperature range package type legacy ordering part number (opn) 2.5 kv only note: all packages are rohs-compliant. moisture sensitivity level is msl3 for wide-body soic -16 and 14-ld lga packages and msl2a for narrow-body soic-16 packages with peak reflow temperatures of 260 c according to the jedec industry standard classifications and peak solder temperatures. free datasheet http:///
si823x 40 rev. 0.3 10. package outline: 16-pin wide body soic figure 46 illustrates the package details for the si823x in a 16-pin wide body soic. table 19 lists the values for the dimensions shown in the illustration. figure 46. 16-pin wide body soic table 19. package diagram dimensions symbol millimeters min max a ? 2.65 a1 0.1 0.3 d 10.3 bsc e 10.3 bsc e1 7.5 bsc b 0.31 0.51 c 0.20 0.33 e 1.27 bsc h 0.25 0.75 l 0.4 1.27 ? 0 7 free datasheet http:///
si823x rev. 0.3 41 11. land pattern: wide-body soic figure 47 illustrates the reco mmended land pattern details for the si823x in a 16-p in wide-body soic. table 20 lists the values for the dimens ions shown in the illustration. figure 47. 16-pin soic land pattern table 20. 16-pin wide body soic land pattern dimensions dimension feature (mm) c1 pad column spacing 9.40 e pad row pitch 1.27 x1 pad width 0.60 y1 pad length 1.90 notes: 1. this land pattern design is based on ipc-7351 pattern soic127p1032x265-16an for density level b (median land protrusion). 2. all feature sizes shown are at maximum material condition (mmc) and a card fabrication tolerance of 0.05 mm is assumed. free datasheet http:///
si823x 42 rev. 0.3 12. package outline: narrow body soic figure 48 illustrates the package details for the si823x in a 16-pin narrow-body soic (so-16). table 21 lists the values for the di mensions shown in the illustration. figure 48. 16-pin small outline integrated circuit (soic) package table 21. package diagram dimensions dimension min max a ? 1.75 a1 0.10 0.25 a2 1.25 ? b 0.31 0.51 c 0.17 0.25 d 9.90 bsc e 6.00 bsc e1 3.90 bsc e 1.27 bsc l 0.40 1.27 l2 0.25 bsc free datasheet http:///
si823x rev. 0.3 43 h 0.25 0.50 0 8 aaa 0.10 bbb 0.20 ccc 0.10 ddd 0.25 notes: 1. all dimensions shown are in m illimeters (mm) unl ess otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec solid state outline ms- 012, variation ac. 4. recommended card reflow profile is per the jedec/ipc j- std-020c specification for small body components. table 21. package diagram dimensions (continued) free datasheet http:///
si823x 44 rev. 0.3 13. land pattern: narrow body soic figure 49 illustrates the recommended land pattern details for the si823x in a 16-pin narrow-body soic. table 22 lists the values for the dimens ions shown in the illustration. figure 49. 16-pin narrow body soic pcb land pattern table 22. 16-pin narrow body soic land pattern dimensions dimension feature (mm) c1 pad column spacing 5.40 e pad row pitch 1.27 x1 pad width 0.60 y1 pad length 1.55 notes: 1. this land pattern design is based on ipc-7351 pattern soic127p600x165-16n for density level b (median land protrusion). 2. all feature sizes shown are at maximum material condition (mmc) and a card fabrication tolerance of 0.05 mm is assumed. free datasheet http:///
si823x rev. 0.3 45 14. package outline: 14 ld lga (5 x 5 mm) figure 50 illustrates the package details for the si823x in an lga outline. table 23 lists the values for the dimensions shown in the illustration. figure 50. si823x lga outline table 23. package diagram dimensions dimension min nom max a 0.74 0.84 0.94 b 0.25 0.30 0.35 d 5.00 bsc d1 4.15 bsc e 0.65 bsc e 5.00 bsc e1 3.90 bsc l 0.70 0.75 0.80 l1 0.05 0.10 0.15 aaa ? ? 0.10 bbb ? ? 0.10 ccc ? ? 0.08 ddd ? ? 0.15 eee ? ? 0.08 notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. free datasheet http:///
si823x 46 rev. 0.3 15. land pattern: 14 ld lga figure 51 illustrates the recomm ended land pattern deta ils for the si823x in a 14-pin lga. table 24 lists the values for the dimensions shown in the illustration. figure 51. 14-pin lga land pattern free datasheet http:///
si823x rev. 0.3 47 table 24. 14-pin lga land pattern dimensions dimension (mm) c1 4.20 e0 . 6 5 x1 0.80 y1 0.40 notes: general: 1. all dimensions shown are in millimeters (mm). 2. this land pattern design is based on the ipc-7351 guidelines. 3. all dimensions shown are at maximu m material condit ion (mmc). least material condition (lmc) is ca lculated based on a fabrication allowance of 0.05 mm. solder mask design: 4. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design: 5. a stainless steel, laser-cut and elec tro-polished stenc il with trapezoidal walls should be used to assure good solder paste release. 6. the stencil thickness should be 0.125 mm (5 mils). 7. the ratio of stencil aperture to land pad size should be 1:1. card assembly: 8. a no-clean, type-3 solder paste is recommended. 9. the recommended card reflow prof ile is per the jedec/ipc j-std- 020d specification for small body components. free datasheet http:///
si823x 48 rev. 0.3 16. package outline: 14 ld lga with thermal pad (5 x 5 mm) figure 52 illustrates the package details for the si8236 isodriver in an lga out line. table 25 lists the values for the dimensions shown in the illustration. figure 52. si823x lga outline with thermal pad table 25. package diagram dimensions dimension min nom max a 0.74 0.84 0.94 b 0.25 0.30 0.35 d 5.00 bsc d1 4.15 bsc e 0.65 bsc e 5.00 bsc e1 3.90 bsc l 0.70 0.75 0.80 l1 0.05 0.10 0.15 p1 1.40 1.45 1.50 p2 4.15 4.20 4.25 aaa ? ? 0.10 bbb ? ? 0.10 ccc ? ? 0.08 ddd ? ? 0.15 eee ? ? 0.08 notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. free datasheet http:///
si823x rev. 0.3 49 17. land pattern: 14 ld lga with thermal pad figure 53 illustrates the recommended la nd pattern details for the si8236 in a 14-pin lga with thermal pad. table 26 lists the values for the dimensions shown in the illustration. figure 53. 14-pin lga with thermal pad land pattern free datasheet http:///
si823x 50 rev. 0.3 table 26. 14-pin lga with thermal pad land pattern dimensions dimension (mm) c1 4.20 c2 1.50 d2 4.25 e0 . 6 5 x1 0.80 y1 0.40 notes: general: 1. all dimensions shown are in millimeters (mm). 2. this land pattern design is based on the ipc-7351 guidelines. 3. all dimensions shown are at maximu m material condit ion (mmc). least material condition (lmc) is calculated based on a fabrication allowance of 0.05 mm. solder mask design: 4. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design: 5. a stainless steel, laser-cut and elec tro-polished stenc il with trapezoidal walls should be used to assure good solder paste release. 6. the stencil thickness should be 0.125 mm (5 mils). 7. the ratio of stencil aperture to land pad size should be 1:1. card assembly: 8. a no-clean, type-3 solder paste is recommended. 9. the recommended card reflow prof ile is per the jedec/ipc j-std- 020d specification for small body components. free datasheet http:///
si823x rev. 0.3 51 d ocument c hange l ist revision 0.11 to revision 0.2 ? updated all specs to reflec t latest silicon revision. ? updated table 1 on page 6 to include new uvlo options. ? updated table 2 on page 10 to reflect new maximum package isolation ratings ? added figures 34, 35, and 36. ? updated ordering guide to reflect new package offerings. ? added "5.6.3.under voltage lockout (uvlo)" on page 25 to describe uvlo operation. revision 0.2 to revision 0.3 ? moved sections 2, 3, and 4 to after section 5. ? updated tables 15, 16, and 17. ?? removed SI8230, si8231, and si8232 from pinout and from title. ? updated and added ordering guide footnotes. ? updated uvlo specifications in table 1 on page 6. ? added pwd and output supply active current specifications in table 1. ? updated and added typical operating condition graphs in "3.typical operating characteristics (0.5 amp)" on page 16 and "4.typical operating characteristics (4.0 amp)" on page 18. free datasheet http:///
si823x 52 rev. 0.3 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. additionally, silicon laboratorie s assumes no responsibility for the functioning of undescribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages. the sale of this product contains no licens es to power-one?s intellectual property. contact power-one, inc. for appropriate lic enses. free datasheet http:///

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